1. Field of the Invention
The present invention relates to a memory device, and more particularly to a power gating circuit of a memory device, a system-on-a-chip (SoC) circuit including the power gating circuit, and a power gating circuit method for reducing a peak current.
2. Description of the Related Art
A typical system-on-a-chip (SoC) circuit consists of one or more microcontroller, microprocessor or DSP cores, memory blocks a ROM and a RAM, timing sources including oscillators and phase-locked loops, voltage regulators and power management circuits. When electric power is applied to a memory device included in a system-on-a-chip circuit, a relatively large current may flow. The large current flows produce heat and may have adversely affect adjacent logic circuits, thereby degrading performance of the system-on-a-chip circuit.
FIG. 1 is a block diagram illustrating a conventional power gating circuit.
Referring to FIG. 1, the conventional power gating circuit includes a power control pin 120 and power gating transistors 130, 140, 150, and 160 that are connected to a power supply voltage (VDD). The power gating transistors 130, 140, 150, and 160 are simultaneously turned ON responding to a power control signal that is applied to the power control pin 120, and thus provide the power supply voltage to a memory device 110. Since the power gating transistors 130, 140, 150, and 160 are all turned ON at the same time, a peak current that is applied to the memory device 110 can be increased abruptly. If the peak current flowing into the memory device 110 is abruptly increased, the current (power) available for operations of the adjacent logic circuits may be limited such that the adjacent logic circuits may operate abnormally.